1. Field of the Invention
This invention relates to an integrated circuit connection system and more specifically to a solid state, three-dimensional integrated circuit system structure.
2. Description of Prior Art
In the formation of the electronics circuits, integrated circuits may be fabricated from thin semiconductor slices having a multiplicity of matrices or microcircuits thereon. The general practice is for each slice to contain a multiple of identical repeating matrices of the same type of microcircuits. The individual unit or circuit is sometimes referred to as an integrated circuit chip or an individual bar.
Before distribution, the present practice is to test each of the circuits of the integrated circuit chip on a slice or wafer prior to separating the slice into the desired integrated circuit components or combinations thereof.
Since each microcircuit or integrated circuit of each wafer is normally positioned in a predetermined, precise relation with respect to adjacent circuit units, it is possible to test the circuitry if probes can be accurately located on each of the preselected points that correspond to circuits to be tested. It is then possible, for example, to test several different circuits at the same time on any one integrated circuit.
In the test procedure there are several obstacles to overcome in order to have reliable testing without damaging the slice. In addition, with the increased complexity of modern integrated circuits, the large number of probes are required to perform adequate tests.
One approach to this problem is a multiprobe test system disclosed in U.S. Pat. No. 4,195,259 by Lee R. Reid. A multiprobe test system was described for testing microcircuits which included a printed circuit board having a plurality of data-detector probes attached for Z axis control and edge detection. A four-quadrant multiprobe edge sensor system was disclosed in U.S. Pat. No. 4,219,771 by Lee R. Reid and Charles R. Ratliff. This system included a printed circuit board having a plurality of data probes mounted thereon which include four data detector probes to detect positioning.
As integrated circuits become more complex, the number of probes required to test these circuits become more numerous. The circuits are also required to operate at higher speeds which introduce several new problems, such as lead inductance and stray capacitance. In addition, the probe needle tip positioning becomes critically sensitive. This invention discloses a technique to interconnect a large number of probes to a relatively small integrated circuit area. The fabrication of multiprobes in a miniature electrical connector is disclosed in the IBM Technical Disclosure Bulletin, "Fabrication of Multiprobe Miniature Electrical Connector", Vol. 19, No. 1, dated June 1976. This article discloses an electrical connector between two silicon wafers that are bonded together having cavities that are filled together with a metal which is liquid at a desired temperature. This type of system was adapted for use in the IBM Josephson System disclosed in Electronics, Nov. 3, 1981, page 40. I/O connections were made to Josephson chips by flexible ribbon cables that included a bottom edge of micropins that plug into mercury-filled wells on a socket. This configuration is only operable, however, at 4.2 degrees Kevin.
Another technique for forming elevated bumps on semiconductor material is disclosed in U.S. Pat. No. 4,182,781 entitled, "Low Cost Method for Forming Elevated Metal Bumps on Integrated Circuit Bodies Employing an Aluminum/Paladium Metallization Base for Electroless Plating" by Robert C. Hooper, et al.
This invention employs the use of elevated contact tips produced by orientation dependent etching of the silicon substrate. A similar etching technique has been disclosed in the article entitled, "High Performance Heat Sinking for VLSI", by D. B. Tuckerman and R. F. Pease in the IEEE Electron Device Letters, Vol. EDL-2, No. 5, published May 1981. This article discloses a method of producing high performance heat sinks where 50 micrometer wide channels with 50 micrometer wide walls were etched vertically using an orientation dependent etch in (110) silicon wafers. The orientation etch of a wafer at the (110) plane results in a series of vertical walls extending from the surface of the wafer.